PIC16F785-I/SS【PDF 48/206 页】IC PIC MCU FLASH 2KX14 20SSOP

收藏本站

您好，
买卖IC网欢迎您。
请登录
免费注册

买卖IC网

Sheet目录3887

44页 45页 46页 47页 [48页]49页 50页 51页 52页

141

8272E–AVR–04/2013

ATmega164A/PA/324A/PA/644A/PA/1284/P

Bit 5 – ICF1: Timer/Counter1, Input Capture Flag

This flag is set when a capture event occurs on the ICP1 pin. When the Input Capture Register

(ICR1) is set by the WGMn3:0 to be used as the TOP value, the ICF1 Flag is set when the coun-

ter reaches the TOP value.

ICF1 is automatically cleared when the Input Capture Interrupt Vector is executed. Alternatively,

ICF1 can be cleared by writing a logic one to its bit location.

Bit 4:3 – Reserved

These bits are unused and will always read as zero.

Bit 2 – OCF1B: Timer/Counter1, Output Compare B Match Flag

This flag is set in the timer clock cycle after the counter (TCNT1) value matches the Output

Compare Register B (OCR1B).

Note that a Forced Output Compare (FOC1B) strobe will not set the OCF1B Flag.

OCF1B is automatically cleared when the Output Compare Match B Interrupt Vector is exe-

cuted. Alternatively, OCF1B can be cleared by writing a logic one to its bit location.

Bit 1 – OCF1A: Timer/Counter1, Output Compare A Match Flag

This flag is set in the timer clock cycle after the counter (TCNT1) value matches the Output

Compare Register A (OCR1A).

Note that a Forced Output Compare (FOC1A) strobe will not set the OCF1A Flag.

OCF1A is automatically cleared when the Output Compare Match A Interrupt Vector is exe-

cuted. Alternatively, OCF1A can be cleared by writing a logic one to its bit location.

Bit 0 – TOV1: Timer/Counter1, Overflow Flag

The setting of this flag is dependent of the WGMn3:0 bits setting. In Normal and CTC modes,

the TOV1 Flag is set when the timer overflows. Refer to Table 16-5 on page 135 for the TOV1

Flag behavior when using another WGMn3:0 bit setting.

TOV1 is automatically cleared when the Timer/Counter1 Overflow Interrupt Vector is executed.

Alternatively, TOV1 can be cleared by writing a logic one to its bit location.

16.12.15 TIFR3 – Timer/Counter3 Interrupt Flag Register

Bit 7:6 – Reserved

These bits are unused and will always read as zero.

Bit 5 – ICF3: Timer/Counter3, Input Capture Flag

This flag is set when a capture event occurs on the ICP3 pin. When the Input Capture Register

(ICR1) is set by the WGMn3:0 to be used as the TOP value, the ICF3 Flag is set when the coun-

ter reaches the TOP value.

ICF3 is automatically cleared when the Input Capture Interrupt Vector is executed. Alternatively,

ICF3 can be cleared by writing a logic one to its bit location.

Bit

76543210

0x18 (0x38)

–

–ICF3

–

OCF3B

OCF3A

TOV3

TIFR3

Read/Write

R/W

Initial Value

00000000

发布紧急采购，3分钟左右您将得到回复。

采购需求

(若只采购一条型号，填写一行即可)

*型号	*数量	厂商	批号	封装

添加更多采购

采购需求

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

我的联系方式